考虑功率约束和恶化效应的并行机器上内存芯片最终测试调度

Scheduling of memory chips for final testing on parallel machines considering power constraints and deteriorating effects

• Shaojun Lu
• Chiwei Hu
• Min Kong 通讯
• Amir M. Fathollahi‐Fard
• Maxim A. Dulebenets 通讯